Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally<1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of. radiation, and such components may also be referred to below, collectively or singularly, as a “lens”. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or the smallest space between two lines. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Currently, various optical proximity correction (OPC) techniques are utilized to allow the resulting image to more accurately correspond to the desired target pattern. A common OPC technique, which is widely known, is the use of subresolution scattering bars (also referred to as assist features). As described, for example, in U.S. Pat. No. 5,821,014, sub-resolution assist features, or scattering bars, are used as a means to correct for optical proximity effects and have been shown to be effective for increasing the overall process window (i.e., the range of focus and exposure dose variation over which features having some specified CD can be printed consistently, regardless of whether or not the features are isolated or densely packed relative to adjacent features). As set forth in the '014 patent, generally speaking, the optical proximity correction occurs by improving the depth of focus for the less dense to isolated features by placing scattering bars near these features. The scattering bars function to change the effective pattern density (of the isolated or less dense features) to be more dense, thereby negating the undesirable proximity effects associated with printing of isolated or less dense features. It is important, however, that the scattering bars themselves do not print on the wafer. Thus, this requires that the size of the scattering bars must be maintained below the resolution capability of the imaging system.
Notwithstanding the wide-spread use of scattering bars, there remains essentially three issues with current scattering bar technology when utilized for patterning feature dimensions at half or below the exposure wavelength. The first issue relates to inadequate protection for the main design features that severely limits focus range. The second issue relates to the fact that in a typical scattering bar solution, too many short pieces of scattering bars are generated which results in excessive demands on mask making capabilities. The third issue relates to the fact that there is no adequate solution for adjacent horizontal and vertical scattering bars to be joined together. Current methods require that the horizontal and vertical scattering bars be pulled apart from one another.
FIGS. 1a-1c illustrate the first issue noted above. FIG. 1a illustrates an exemplary layout having both features to be printed 12 and scattering bars 13 which perform OPC. FIGS. 1b and 1c illustrate the resulting printing performance at “best focus” and a defocus of 0.1 um. As shown in FIG. 1c, which has a portion of the resulting pattern encircled which corresponds to the encircled portion of the mask of FIG. 1a, the areas 14 of features 12 which do not have any vertically positioned scattering bars adjacent thereto exhibit “pinching” (i.e., a undesirable reduction in the width of the line to be printed).
FIG. 2 illustrates the second issue noted above. More specifically, FIG. 2 illustrates a mask (also referred to herein as mask layout) modified to include scattering bars utilizing currently known techniques for scattering bar application. The mask includes both features 12 to be printed and scattering bars 13. As shown in FIG. 2, current techniques result in an excessive number of short pieces of scattering bars 15 in the mask layout. However, due to mask making process limitations, many of these short pieces of scattering bars must be eliminated, thereby undesirably reducing printing performance.
FIG. 2 also illustrates the third issue noted above. As shown, none of the vertical and horizontal scattering bars 13 located proximate one another are connected to one another. This is due to the fact that current techniques for placing scattering bars within a mask design require that vertical and horizontal scattering bars, for example, which are adjacent a corner of a feature to be printed, be pulled apart from one another so as to prevent imaging of the intersecting portion of the scattering bars. However, as noted above, the elimination of scattering bar portions from the mask results in an undesirable reduction in printing performance.
Thus, there exists a need for a method of providing subresolution scattering bars (also referred to as assist features) in a mask which overcomes the foregoing problems so as to allow for improved OPC and printing performance.
The following description discusses novel methods for applying scattering bars to a mask layout.